R
Virtex-II Platform FPGAs: DC and Switching Characteristics
IOB Input Switching Characteristics Standard Adjustments
Table 15 gives all standard-specific data input delay adjustments.
Table 15: IOB Input Switching Characteristics Standard Adjustments
Speed Grade
IOSTANDARD
Timing
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
Attribute
Parameter
-6
-5
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL
T
0.00
0.00
0.11
0.42
0.98
0.60
0.60
0.68
0.56
0.48
0.68
0.48
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.42
0.98
0.00
0.00
0.11
0.43
1.00
0.60
0.60
0.69
0.56
0.49
0.69
0.49
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.43
1.00
0.00
0.00
0.12
0.49
1.15
0.69
0.69
0.79
0.65
0.56
0.79
0.56
0.69
0.00
0.00
0.00
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.40
0.00
0.12
0.49
1.14
ILVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVDS_25
LVDS_33
LVDSEXT_25
LVDSEXT_33
ULVDS_25
BLVDS_25
LDT_25
T
ILVCMOS33
T
ILVCMOS25
LVCMOS, 1.8V
T
ILVCMOS18
LVCMOS, 1.5V
T
ILVCMOS15
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
T
ILVDS_25
T
ILVDS_33
LVDSEXT (Extended Mode), 2.5V
LVDSEXT, 3.3V
T
ILVDSEXT_25
ILVDSEXT_33
T
ULVDS (Ultra LVDS), 2.5V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
T
T
IULVDS_25
IBLVDS_25
T
ILDT_25
LVPECL_33
PCI33_3
T
ILVPECL_33
T
IPCI33_3
PCI66_3
T
IPCI66_3
PCI-X, 133 MHz, 3.3V
PCIX
T
IPCIX
GTL (Gunning Transceiver Logic)
GTL Plus
GTL
T
IGTL
GTLP
T
IGTLP
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL_I
T
IHSTL_I
HSTL_II
T
IHSTL_II
HSTL, Class III
HSTL_III
T
IHSTL_III
HSTL, Class IV
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III_18
HSTL_IV_18
SSTL18_I
SSTL18_II
SSTL2_I
T
IHSTL_IV
HSTL, Class I, 1.8V
T
T
IHSTL_I_18
HSTL, Class II, 1.8V
IHSTL_II_18
IHSTL_III_18
HSTL, Class III, 1.8V
T
T
HSTL, Class IV, 1.8V
IHSTL_IV_18
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
T
ISSTL18_I
T
ISSTL18_II
SSTL, Class I, 2.5V
T
ISSTL2_I
SSTL, Class II, 2.5V
SSTL2_II
SSTL3_I
T
ISSTL2_II
SSTL, Class I, 3.3V
T
ISSTL3_I
SSTL, Class II, 3.3V
SSTL3_ II
AGP
T
ISSTL3_II
AGP-2X/AGP (Accelerated Graphics Port)
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
T
IAGP
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
T
ILVDCI_33
T
ILVDCI_25
LVDCI, 1.8V
T
ILVDCI_18
LVDCI, 1.5V
T
ILVDCI_15
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
11
XILINX [ XILINX, INC ]
