R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
XQ4000XL Global Low Skew Clock, Set-Up and Hold
Speed Grade
Device
-3
-1
Units
Description
Input Setup and Hold Times Using
Global Low Skew Clock and IFF
No Delay
Symbol
Min
Min
T
/T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 3.2
1.2 / 5.5
1.2 / 7.0
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PSN PHN
0.9 / 7.1
Partial Delay
T
/T
6.1 / 0.0
6.4 / 1.0
6.7 / 1.2
-
-
-
-
PSP PHP
9.8 / 1.2
Full Delay
T
/T
6.4 / 0.0
6.6 / 0.0
6.8 / 0.0
-
-
-
-
PSD PHD
9.6 / 0.0
IFF = Input Flip-Flop or Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest
distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to deter-
mine the setup and hold times under given design conditions.
DS029 (v1.2) February 9, 2000
11
XILINX [ XILINX, INC ]
