R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade
Device
-3
-1
Description
Input Setup and Hold Times
No Delay
Global Early Clock and IFF
Global Early Clock and FCL
Symbol
Min
Min
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
-
-
T
T
/T
PSEN PHEN
/T
PFSEN PFHEN
0.9 / 6.6
Partial Delay
Global Early Clock and IFF
Global Early Clock and FCL
5.4 / 0.0
6.4 / 0.8
8.4 / 1.5
-
-
-
-
T
T
/T
PSEP PHEP
/T
PFSEP PFHEP
11.0 / 0.0
Full Delay
Global Early Clock and IFF
12.0 / 0.0
13.8 / 0.0
13.1 / 0.0
-
-
-
-
T
/T
PSED PHED
13.6 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest dis-
tance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the
setup and hold times under given design conditions.
12
DS029 (v1.2) February 9, 2000
XILINX [ XILINX, INC ]
