R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Speed Grade
Size Symbol
-3
-1
Unit
s
Dual Port RAM
Write Operation
Min Max Min Max
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
T
T
T
T
T
T
T
T
T
9.0
4.5
2.5
0
2.5
0
7.7
3.9
1.7
0
2.0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCDS
WPDS
ASDS
AHDS
DSDS
DHDS
WSDS
WHDS
WODS
1.8
0
1.6
0
7.8
6.7
Note 1: Timing for16 x1 RAM option is identical to16 x 2 RAM.
DS029 (v1.2) February 9, 2000
7
XILINX [ XILINX, INC ]
