R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
XQ4000XL Output Flip-Flop, Clock to Out
Speed Grade
Device
-3
-1
Units
Description
Symbol
Max
Max
Global Low Skew Clock to Output using OFF
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
8.6
9.8
11.3
-
-
-
-
ns
ns
ns
ns
ICKOF
9.5
Global Early Clock to Output using OFF
Values are for BUFGE #s 3, 4, 7, and 8. Add
1.4 ns for BUFGE #s 1, 2, 5, and 6.
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
7.4
8.1
9.9
-
-
-
-
ns
ns
ns
ns
ICKEOF
8.5
For output SLOW option add
OFF = Output Flip Flop
T
All Devices
3.0
3.0
ns
SLOW
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads,
see graph below.
XQ4000XL Output Mux, Clock to Out
Speed Grade
Device
-3
-1
Units
Description
Symbol
Max
Max
Global Low Skew Clock to Output using OFF
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
8.8
10.0
11.4
-
-
-
-
ns
ns
ns
ns
ICKOF
ICKEOF
SLOW
Global Early Clock to Output using OFF. Val- T
ues are for BUFGE #s 3, 4, 7, and 8. Add 1.4
ns for BUFGE #s 1, 2, 5, and 6.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
7.6
8.2
10.0
-
-
-
-
ns
ns
ns
ns
For output SLOW option add
OFF = Output Flip Flop
T
All Devices
3.0
3.0
ns
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads,
see graph below.
DS029 (v1.2) February 9, 2000
9
XILINX [ XILINX, INC ]
