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5962-9850901QZB 参数 Datasheet PDF下载

5962-9850901QZB图片预览
型号: 5962-9850901QZB
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, CQFP228, CERAMIC, QFP-228]
分类和应用: 可编程逻辑
文件页数/大小: 19 页 / 543 K
品牌: XILINX [ XILINX, INC ]
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R
QPROXQ4000XL Series QML High-Reliability FPGAs  
XQ4000XL IOB Input Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%  
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are  
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the  
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path  
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume  
worst-case operating conditions (supply voltage and junction temperature).  
Speed Grade  
Device  
-3  
-1  
Units  
Description  
Symbol  
Min  
Min  
Clocks  
Clock Enable (EC) to Clock (IK)  
Delay from FCL enable (OK) active edge to IFF clock (IK)  
active edge  
T
T
All devices  
All devices  
0.3  
1.7  
0.3  
1.7  
ns  
ns  
ECIK  
OKIK  
Setup Times  
Pad to Clock (IK), no delay  
Pad to Clock (IK), via transparent Fast Capture Latch, no  
delay  
T
T
All devices  
All devices  
1.7  
2.3  
1.7  
2.3  
ns  
ns  
PICK  
PICKF  
Pad to Fast Capture Latch Enable (OK), no delay  
Hold Times  
T
All devices  
All devices  
0.7  
0
0.7  
0
ns  
ns  
POCK  
All Hold Times  
Global Set/Reset  
Minimum GSR Pulse Width  
Delay from GSR input to any Q  
T
T
All devices  
XQ4013XL  
XQ4036XL  
XQ4062XL  
XQ4085XL  
19.8  
15.9  
22.5  
29.1  
-
19.8  
-
-
ns  
ns  
ns  
ns  
ns  
MRW  
RRI  
-
26.0  
Max  
1.6  
2.6  
3.1  
1.8  
1.9  
3.6  
Propagation Delays  
Max  
1.6  
Pad to I1, I2  
T
T
All devices  
All devices  
All devices  
All devices  
All devices  
All devices  
ns  
ns  
ns  
ns  
ns  
ns  
PID  
PLI  
Pad to I1, I2 via transparent input latch, no delay  
2.6  
Pad to I1, I2 via transparent FCL and input latch, no delay T  
3.1  
PFLI  
Clock (IK) to I1, I2 (flip-flop)  
T
T
T
1.8  
1.9  
3.6  
IKRI  
IKLI  
Clock (IK) to I1, I2 (latch enable, active Low)  
FCL Enable (OK) active edge to I1, I2  
(via transparent standard input latch)  
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch  
OKLI  
14  
DS029 (v1.2) February 9, 2000  
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