R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade
Symbol
-3
-1
Units
Description
Min
Max
Min
Max
Clocks
Clock High
Clock Low
T
T
3.0
3.0
2.5
2.5
ns
ns
CH
CL
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
T
T
T
T
T
T
5.0
4.1
4.4
4.1
5.5
5.1
3.8
3.1
3.0
3.3
4.2
3.9
ns
ns
ns
ns
ns
ns
OKPOF
OPF
TSHZ
TSONF
OFPF
OKFPF
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
T
T
T
T
0.5
0.0
0.0
0.3
0.3
0.0
0.0
0.1
ns
ns
ns
ns
OOK
OKO
ECOK
OKEC
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XQ4013XL
T
T
19.8
15.0
ns
MRW
RPO
20.5
27.1
33.7
-
-
-
-
ns
ns
ns
ns
XQ4036XL
XQ4062XL
XQ4085XL
29.5
Slew Rate Adjustment
For output SLOW option add
T
3.0
2.0
ns
SLOW
Note 1: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.
DS029 (v1.2) February 9, 2000
15
XILINX [ XILINX, INC ]
