R
XC4000E and XC4000X Series Field Programmable Gate Arrays
C
OUT
M
G1
M
1
0
1
G2
G3
0
I
G4
C
OUT0
TO
FUNCTION
GENERATORS
M
F2
F1
M
1
0
0
1
M
F4
M
M
0
1
3
1
0
F3
M
M
M
M
1
0
C
INUP
C
X2000
IN DOWN
Figure 14: Detail of XC4000E Dedicated Carry Logic
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising edge
triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be imple-
mented in a single IOB, as described in the XACT Libraries
Guide.
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 15 shows a simplified block diagram of the
XC4000E IOB. A more complete diagram which includes
the boundary scan logic of the XC4000E IOB can be found
in Figure 40 on page 43, in the “Boundary Scan” section.
The XC4000E inputs can be globally configured for either
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
the bitstream generation software. There is a slight input
hysteresis of about 300mV. The XC4000E output levels are
also configurable; the two global adjustments of input
threshold and output level are independent.
The XC4000X IOB contains some special features not
included in the XC4000E IOB. These features are high-
lighted in a simplified block diagram found in Figure 16, and
discussed throughout this section. When XC4000X special
features are discussed, they are clearly identified in the
text. Any feature not so identified is present in both
XC4000E and XC4000X devices.
Inputs on the XC4000XL are TTL compatible and 3.3V
CMOS compatible. Outputs on the XC4000XL are pulled to
the 3.3V positive supply.
The inputs of XC4000 Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
IOB Input Signals
Two paths, labeled I1 and I2 in Figure 15 and Figure 16,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an
edge-triggered flip-flop or a level-sensitive latch.
Supported sources for XC4000 Series device inputs are
shown in Table 8.
6-20
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
