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X24F064S-5 参数 Datasheet PDF下载

X24F064S-5图片预览
型号: X24F064S-5
PDF下载: 下载PDF文件 查看货源
内容描述: SerialFlash TM记忆带座锁TM保护 [SerialFlash TM Memory with Block Lock TM Protection]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 18 页 / 87 K
品牌: XICOR [ XICOR INC. ]
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X24F064/032/016
DEVICE OPERATION
The X24F064/032/016 supports a bidirectional bus ori-
ented protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the re-
ceiving device as the receiver. The device controlling
the transfer is a master and the device being controlled
is the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and receive
operations. Therefore, the X24F064/032/016 will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24F064/032/016 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition has
been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
6686 ILL F04
Notes:
(5) Typical values are for T
A
= 25
°
C and nominal supply voltage (2.7V)
(6) t
PR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal program operation.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
6686 ILL F05
3