X24F064/032/016
Sequential Read
The data output is sequential, with the data from
address n followed by the data from n + 1. The
address counter for read operations increments all
address bits, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space, the counter “rolls over” to 0 and the
X24F064/032/016 continues to output data for each
acknowledge received. Refer to Figure 8 for the
address, acknowledge and data transfer sequence.
Sequential reads can be initiated as either a current
address read or random access read. The first byte is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24F064/032/016
continues to output data for each acknowledge
received. The read operation is terminated by the
master; by not responding with an acknowledge and
then issuing a stop condition.
Figure 8. Sequential Read
S
SLAVE
ADDRESS
T
O
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
P
A
C
K
BUS ACTIVITY:
X24F016/032/064
DATA n
DATA n+1
DATA n+2
DATA n+x
6686 ILL F13.1
Figure 9. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
6686 ILL F14
8
XICOR [ XICOR INC. ]
