X24128
WRITE PROTECT REGISTER (WPR)
Writing to the Write Protect Register
BL0, BL1: Block Lock Protect Bits (Nonvolatile)
The Block Lock Protect Bits, BL0 and BL1, determine
which blocks of the array are protected. A write to a
protected block of memory is ignored, but will receive
an acknowledge. The master must issue a stop to put
the part into standby, just as it would for a valid write;
but the stop will not initiate an internal nonvolatile write
cycle. See Table 1.
The Write Protect Register can only be modified by
performing a “Byte Write” operation directly to the
address FFFFh as described below.
The Data Byte must contain zeroes where indicated in
the procedural descriptions below; otherwise the oper-
ation will not be performed. Only one Data Byte is
allowed for each register write operation. The part will
not acknowledge any data bytes after the first byte is
entered. The user then has to issue a stop to initiate
the nonvolatile write cycle that writes BL0, BL1, and
WPEN to the nonvolatile bits. A stop must also be
issued after volatile register write operations to put the
device into Standby.
WPEN: Write Protect Enable Bit (Nonvolatile)
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Write Protect Register control
the Programmable Hardware Write Protection feature.
Hardware Write Protection is enabled when the WP pin
is HIGH and the WPEN bit is HIGH, and disabled when
either the WP pin is LOW or the WPEN bit is LOW. Fig-
ure 12 defines the write protect status for each combi-
nation of WPEN and WP. When the chip is Hardware
Write Protected, nonvolatile writes are disabled to the
Write Protect Register, including the Block Lock protect
bits and the WPEN bit itself, as well as to the Block
Lock protected sections in the memory array. Only the
sections of the memory array that are not Block Lock
protected, and the volatile bits WEL and RWEL, can be
written.
The state of the Write Protect Register can be read by
performing a random byte read at FFFFh at any time.
The part will reset itself after the first byte is read. The
master should supply a stop condition to be consistent
with the protocol, but a stop is not required to end this
operation. After the read, the address counter contains
0000h.
Write Protect Register: WPR (ADDR = FFFF )
h
In Circuit Programmable ROM Mode
7
6
5
4
3
2
1
0
Note that when the WPEN bit is write protected, it can-
not be changed back to a LOW state; so write protec-
tion is enabled as long as the WP pin is held HIGH.
Thus an In Circuit Programmable ROM function can be
WPEN
0
0
BL1 BL0 RWEL WEL
0
WEL: Write Enable Latch (Volatile)
0 = Write Enable Latch reset, writes disabled.
implemented by hardwiring the WP pin to V , writing
CC
to and Block Locking the desired portion of the array to
be ROM, and then programming the WPEN bit HIGH.
1 = Write Enable Latch set, writes enabled.
RWEL: Register Write Enable Latch (Volatile)
Unused Bit Positions
0 = Register Write Enable Latch reset, writes to the
Write Protect Register disabled.
Bits 0, 5 & 6 are not used. All writes to the WPR must
have zeros in these bit positions. The data byte output
during a WPR read will contain zeros in these bits.
1 = Register Write Enable Latch set, writes to the Write
Protect Register enabled.
Characteristics subject to change without notice. 8 of 16
REV 1.1 9/8/00
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