X24128
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
DEVICE ADDRESSING
Figure 4. Device Addressing
Following a start condition, the master must output the
address of the slave it is accessing.The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S0, S1, and S2. This allows up to 8
devices to share a single bus.These bits are compared
to the S0, S1, and S2 device select input pins. The last
bit of the Slave Address Byte defines the operation to
be performed. When the R/W bit is a one, then a read
operation is selected. When it is zero then a write oper-
ation is selected. Refer to Figure 4. After loading the
Slave Address Byte from the SDA bus, the device com-
pares the device type bits with the value “1010” and the
device select bits with the status of the device select
input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle and
the device returns to the standby mode.
Device Type
Identifier
Device
Select
1
0
1
0
S
2
S
1
S
R/W
0
Slave Address Byte
High Order Word Address
0
0
A13 A12 A11 A10 A9 A8
X24128 Word Address Byte 1
Low Order Word Address
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
A7
A6
A4 A3
A2 A1
A0
A5
Word Address Byte 0
The internal organization of the E2 array is 512 pages
by 32 bytes per page. The page address is partially con-
tained in the Word Address Byte 1 and partially in bits 7
through 5 of the Word Address Byte 0.The byte address
is contained in bits 4 through 0 of the Word Address
Byte 0. See Figure 4.
D7 D6 D5
D4 D3
D2 D1 D0
Data Byte
Characteristics subject to change without notice. 4 of 16
REV 1.1 9/8/00
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