X24128
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
DH
AA
BUF
SDA OUT
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(7)
Max.
Unit
(8)
WC
T
Write Cycle Time
5
10
ms
Notes: (7) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(8) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WR
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24128 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Bus Timing
SCL
8th Bit
ACK
SDA
Word n
t
WR
STOP
Condition
START
Condition
Characteristics subject to change without notice. 12 of 16
REV 1.1 9/8/00
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XICOR [ XICOR INC. ]
