X24128
WRITE OPERATIONS
Byte Write
after the first data word is transferred, the master can
transmit up to thirty-one more words. The device will
respond with an acknowledge after the receipt of each
word, and then the byte address is internally incremented
by one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to the first byte of the current page. This
means that the master can write 32 words to the page
beginning at any byte. If the master begins writing at byte
16, and loads 32 words, then the first 16 words are writ-
ten to bytes 16 through 31, and the last 16 words are writ-
ten to bytes 0 through 15. Afterwards, the address
counter would point to byte 16. If the master writes more
than 32 words, then the previously loaded data is over-
written by the new data, one byte at a time.
For a write operation, the device requires the Slave
Address Byte, the Word Address Byte 1, and the Word
Address Byte 0, which gives the master access to any
one of the words in the array. Upon receipt of the Word
Address Byte 0, the device responds with an acknowl-
edge, and waits for the first eight bits of data. After
receiving the 8 bits of the data byte, the device again
responds with an acknowledge. The master then termi-
nates the transfer by generating a stop condition, at
which time the device begins the internal write cycle to
the nonvolatile memory. While the internal write cycle
is in progress the device inputs are disabled and the
device will not respond to any requests from the master.
The SDA pin is at high impedance. See Figure 5.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the inter-
nal write cycle. Refer to Figure 6 for the address,
acknowledge, and data transfer sequence.
Page Write
The device is capable of a thirty-two byte page write oper-
ation. It is initiated in the same manner as the byte write
operation; but instead of terminating the write operation
Figure 5. Byte Write Sequence
S
S
T
A
R
T
Word Address
Byte 1
Word Address
Byte 0
Signals from
the Master
Slave
Address
T
O
P
Data
S 1 0 1 0
0
P
SDA Bus
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 6. Page Write Sequence
(0 ≤ n ≤ 31)
S
T
A
R
T
Word Address
Byte 1
Word Address
Byte 0
Data
(0)
Data
(n)
Slave
Address
S
T
O
P
Signals from
the Master
SDA Bus
1 0 1 0
S
P
0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Characteristics subject to change without notice. 5 of 16
REV 1.1 9/8/00
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