X24128
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues another
start condition and the Slave Address Byte with the R/
W bit set to one. This is followed by an acknowledge
and then eight bits of data from the device. The master
terminates the read operation by not responding with
an acknowledge, and then issuing a stop condition.
Refer to Figure 9 for the address, acknowledge, and
data transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the sec-
ond start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the address
counter, but no data is output by the device.
Figure 9. Random Read Sequence
S
T
A
R
T
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
S
T
A
R
T
S
A
C
K
A
C
K
A
C
K
Slave
Address
1
A
C
K
Data
S
T
O
P
P
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to out-
put data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter “rolls over” to address
0000h, and the device continues to output data for
each acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
Signals from
the Master
SDA Bus
Signals from
the Slave
S 1 0 1 0
0
Figure 10. Sequential Read Sequence
Signals from
the Master
S
T
O
P
P
A
C
K
Slave
Address
S
1
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Data
(1)
Data
(2)
Data
(n–1)
Data
(n)
(n is any integer greater than 1)
REV 1.1 9/8/00
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Characteristics subject to change without notice.
7 of 16
XICOR [ XICOR INC. ]
