X24128
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the inter-
nal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned, and the host can then proceed
with the read or write operation. Refer to Figure 7.
Figure 7. Acknowledge Polling Sequence
Byte LoAd Completed
By Issuing Stop.
Enter ACK Polling
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock, and then
issues a stop condition. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
Issue
START
Issue Slave
Address Byte
(Read or Write)
Issue STOP
ACK
Returned?
Yes
No
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 8. Current Address Read Sequence
Signals from
the Master
S
T
A
R
T
High
Voltage
Cycle Complete.
Continue
Sequence?
No
Slave
Address
1
A
C
K
Data
S
T
O
P
P
SDA Bus
Signals from
the Slave
Issue STOP
S 1 0 1 0
Yes
Continue Normal
Read or Write
Command Sequence
PROCEED
REV 1.1 9/8/00
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Characteristics subject to change without notice.
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