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X24128S14I-2.5T1 参数 Datasheet PDF下载

X24128S14I-2.5T1图片预览
型号: X24128S14I-2.5T1
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 16KX8, Serial, CMOS, PDSO14, PLASTIC, SOIC-14]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 16 页 / 142 K
品牌: XICOR [ XICOR INC. ]
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X24128
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
START Bit
STOP Bit
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
REV 1.1 9/8/00
www.xicor.com
Characteristics subject to change without notice.
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