X1241 – Preliminary Information
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Bit
Range
7
6
5
4
3
2
1
0
(optional)
Factory
Settings
003F
0037
0036
0035
0034
0033
0032
0031
0030
0010
Status
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
BAT
0
0
Y23
0
0
MIL
0
0
BP2
X
0
0
Y22
0
0
0
M22
S22
BP1
X
Y2K21
0
Y21
0
D21
H21
M21
S21
BP0
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
WD1
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
WD0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
0
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
0
19/20
0-6
0-99
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
RTC (SRAM)
Control
(EEPROM)
BL
REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
The X1241 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Day of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven days
of the week. The counter advances in the cycle 0-1-2-
3-4-5-6-0-1-2-... The assignment of a numerical value
to a specific day of the week is arbitrary and may be
decided by the system software designer. The Clock
Default values define 0=Sunday.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date)
is 1 to 31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
24-Hour Time
If the MIL bit of the HR register is 1, the RTC will use a
24-hour format. If the MIL bit is 0, the RTC will use
12-hour format and bit H21 will function as an AM/PM
indicator with a ‘1’ representing PM. The clock defaults
to Standard Time with H21 = 0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1241 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, and read a Low Voltage Sense bit. This regis-
ter is logically separated from both the array and the
Clock/Control Registers (CCR).
Table 2. Status Register (SR)
Addr
003Fh
Default
7
BAT
0
6
0
0
5
0
0
4
0
0
3
0
0
2
RWEL
0
1
WEL
0
0
RTCF
1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V
BACK
, not V
CC
. It is a read only bit and is set/
reset by hardware.
REV 1.1.3 2/13/01
www.xicor.com
Characteristics subject to change without notice.
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