WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R56 (38h)
Clocking 4
8:5
CLK_DCS_DIV[3:0]
1000
Clock divider control for DC Servo, set to get 1.5Mhz from SYSCLK
0000 : SYSCLK/1
0001 : SYSCLK/1.5
0010 : SYSCLK/2
0011 : Reserved
0100 : SYSCLK/3
0101 : SYSCLK/4
0110 : SYSCLK/5.5
0111 : SYSCLK/6
1000 : SYSCLK/8
1001-1111 : Reserved
Specifies the rate of SYSCLK with respect to the sample rate.
4:1
CLK_SYS_RATE[3:0]
0011
0000 : 64*fs
0001 : 128*fs
0010 : 192*fs
0011 : 256*fs
0100 : 384*fs
0101 : 512*fs
0110 : 768*fs
0111 : 1024 *fs
1000 : 1408*fs
1001 : 1536*fs
1010 -> 1111 : reserved
Register 38h Clocking 4
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Controls volume of ADC Right side tone, 3dB steps.
R57 (39h)
DSP
7:4
ADCR_DAC_SVOL[3:0]
0000
0000 : -36dB
0001 : -33dB
…
Sidetone 0
1111 : 0dB
DAC Right Side-tone Control
11 = Unused
3:2
ADC_TO_DACR[1:0]
00
10 = Mix ADCR into DACR
01 = Mix ADCL into DACR
00 = No Side-tone mix into DACR
Register 39h DSP Sidetone 0
PP, August 2009, Rev 3.1
w
95
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
