Pre-Production
WM8959
CONTROL INTERFACE TIMING – 4-WIRE MODE
4-wire mode supports readback via SDOUT which is available as a GPIO pin function.
t
CSU
CSB
t SCY
t CHO
SCLK
SDIN
LSB
t DSU
t DHO
Figure 10 Control Interface Timing – 4-Wire Serial Control Mode (Write Cycle)
CSB
SCLK
SDOUT
LSB
t DL
Figure 11 Control Interface Timing – 4-Wire Serial Control Mode (Read Cycle)
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=HPVDD=SPKVDD=3.3V, DGND=AGND=HPGND=SPKGND=0V, TA =+25oC, Slave Mode,
fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB falling edge
SCLK falling edge to CSB rising edge
SCLK pulse cycle time
SYMBOL
MIN
TYP
MAX
UNIT
tCSU
tCHO
tSCY
tSCL
tSCH
tDSU
tDHO
tDL
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
80
SCLK pulse width low
SCLK pulse width high
80
SDIN to SCLK set-up time
40
SDIN to SCLK hold time
10
SDOUT propagation delay from SCLK rising edge
Pulse width of spikes that will be suppressed
SCLK falling edge to SDOUT transition
10
5
tps
0
tDL
40
PP, May 2008, Rev 3.1
31
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
