WM8959
Pre-Production
CONTROL INTERFACE TIMING – 3-WIRE MODE
3-wire mode is selected by connecting the MODE pin high.
Figure 8 Control Interface Timing – 3-Wire Serial Control Mode (Write Cycle)
CSB
SCLK
SDOUT
LSB
t DL
Figure 9 Control Interface Timing – 3-Wire Serial Control Mode (Read Cycle)
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=HPVDD=SPKVDD=3.3V, DGND=AGND=HPGND=SPKGND=0V, TA=+25oC, Slave Mode,
fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
CSB falling edge to SCLK rising edge
SCLK falling edge to CSB rising edge
SCLK pulse cycle time
SYMBOL
MIN
TYP
MAX
UNIT
tCSU
tCHO
tSCY
tSCL
tSCH
tDSU
tDHO
tps
40
40
200
80
80
40
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SDIN to SCLK hold time
Pulse width of spikes that will be suppressed
SCLK falling edge to SDOUT transition
5
tDL
40
PP, May 2008, Rev 3.1
30
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
