WM8959
Pre-Production
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 6 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK (or BCLK2) cycle time
SYMBOL
MIN
TYP
MAX
UNIT
tBCY
tBCH
tBCL
50
20
20
20
ns
ns
ns
ns
BCLK (or BCLK2) pulse width high
BCLK (or BCLK2) pulse width low
DACLRC (or DACLRC2) set-up time to BCLK (or BCLK2)
rising edge
tLRSU
DACLRC (or DACLRC2) hold time from BCLK (or BCLK2)
rising edge
tLRH
tDH
tDS
10
10
20
ns
ns
ns
DACDAT (or DACDAT2) hold time from BCLK (or BCLK2)
rising edge
DACDAT (or DACDAT2) set-up time to BCLK (or BCLK2)
rising edge
Note:
BCLK (or BCLK2) period should always be greater than or equal to MCLK period.
PP, May 2008, Rev 3.1
28
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
