Pre-Production
WM8959
AUDIO INTERFACE TIMING – MASTER MODE
Figure 5 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs,
data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
DACLRC (or DACLRC2) propagation delay from BCLK (or
BCLK2) falling edge
tDL
20
ns
DACDAT (or DACDAT2) setup time to BCLK rising edge
DACDAT (or DACDAT2) hold time from BCLK rising edge
tDST
tDHT
20
10
ns
ns
PP, May 2008, Rev 3.1
27
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