Pre-Production
WM8959
Figure 14 Typical Power up Sequence where DCVDD is powered before AVDD
Figure 14 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that
DCVDD is already up to specified operating voltage. When AVDD goes above the minimum
threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the
chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises
to Vpora_on, PORB is released high and all registers are in their default state and writes to the control
interface may take place.
On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the
minimum threshold Vpord_off
.
SYMBOL
Vpora
MIN
TYP
0.6
MAX
UNIT
V
V
V
V
V
Vpora_on
Vpora_off
Vpord_on
Vpord_off
1.52
1.5
0.92
0.9
Table 1 Typical POR Operation (typical values, not tested)
Notes:
1. If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating
level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal
operation when the voltage is back to the recommended level again.
2. The chip will enter reset at power down when AVDD or DCVDD falls below Vpora_off or Vpord_off
.
This may be important if the supply is turned on and off frequently by a power management
system.
3. The minimum tpor period is maintained even if DCVDD and AVDD have zero rise time. This
specification is guaranteed by design rather than test.
PP, May 2008, Rev 3.1
33
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
