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WM8959 参数 Datasheet PDF下载

WM8959图片预览
型号: WM8959
PDF下载: 下载PDF文件 查看货源
内容描述: 移动多媒体DAC,具有双模式AB / D类扬声器驱动器 [Mobile Multimedia DAC with Dual-Mode Class AB/D Speaker Driver]
分类和应用: 驱动器
文件页数/大小: 155 页 / 2044 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8959  
Pre-Production  
DEVICE DESCRIPTION  
INTRODUCTION  
The WM8959 is a low power, high quality audio DAC designed to interface with a wide range of  
processors and analogue components. A high level of mixed-signal integration in a very small 3.226  
x 3.44mm footprint makes it ideal for portable applications such as mobile phones.  
Eight highly flexible analogue inputs allow interfacing to up to four microphone inputs plus multiple  
stereo or mono line inputs (single-ended or differential). Connections to an external voice CODEC,  
FM radio, melody IC, line input, handset MIC and headset MIC are all fully supported. Signal routing  
to the output mixers and within the DAC has been designed for maximum flexibility to support a wide  
variety of usage modes.  
Ten analogue output drivers are integrated, including a high power, high quality speaker driver,  
capable of providing 1W in class D mode or in class AB mode into 8BTL. Four headphone drivers  
are provided, supporting ear speakers and stereo headsets. Fully differential headphone drive is  
supported for excellent crosstalk performance and removing the need for large and expensive  
headphone capacitors. Four line outputs are available for Tx voice output to a voice CODEC,  
interfacing to an additional speaker driver and single-ended or fully differential line output. All outputs  
have integrated pop and click suppression. The speaker supply has been designed with low leakage  
and high PSRR, to support direct connection to a Lithium battery. In addition to the speaker PGA, six  
AC and DC gain settings allow output signal level to be maximised for many commonly-used  
SPKVDD/AVDD combinations.  
Internal signal routing and amplifier configurations have been optimised to provide the lowest  
possible power consumption for a number of common usage scenarios such as voice calls and  
music playback.  
The stereo DACs are of hi-fi quality using a 24-bit, low-order oversampling architecture to deliver  
optimum performance. An integrated ultra-low power PLL provides flexible clocking capabilities. DAC  
soft mute and un-mute is available for pop-free music playback.  
The WM8959 has a highly flexible digital audio interface, supporting a number of protocols, including  
I2S, DSP, MSB-First left/right justified. The interface can operate in master or slave modes. PCM  
operation is supported in the DSP mode. A-law and µ-law companding are also supported. Time  
division multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on  
the same bus, saving space and power. Alternative DAC interface pins are provided to allow  
connection to an additional processor.  
The SYSCLK (system clock) provides clocking for the DACs, DSP, Class D outputs and the digital  
audio interface. SYSCLK can be derived directly from the MCLK pin or via the integrated PLL,  
providing flexibility to support a wide range of clocking schemes. All MCLK frequencies typically used  
in portable systems are supported for sample rates between 8kHz and 48kHz. A flexible switching  
clock for the class D speaker drivers (synchronous with the audio DSP clocks for best performance)  
is also derived from SYSCLK.  
To allow full software control over all its features, the WM8959 uses a standard 2-wire or 3/4-wire  
control interface with readback of key registers supported. It is fully compatible and an ideal partner  
for a wide range of industry standard microprocessors, controllers and DSPs. Unused circuitry can  
be disabled via software to save power, while low leakage currents extend standby and off time in  
portable battery-powered applications. The device address can be selected using the CSB/ADDR  
pin.  
Versatile GPIO functionality is provided, with support for up to four button/accessory detect inputs  
with interrupt and status readback and flexible de-bouncing options, clock output, and logic '1' / logic  
'0' for control of additional external circuitry.  
PP, May 2008, Rev 3.1  
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