Pre-Production
WM8959
The required settings for this example are:
•
•
•
•
•
•
MCLK_DIV = 10b
PRESCALE = 0b
PLL_ENA = 1
SDM = 1
PLLN = 8 = 8h
PLLK = 0.192 = 3126h
EXAMPLE PLL SETTINGS
Table 65 provides example PLL settings for generating common SYSCLK frequencies from a variety
of MCLK reference frequencies.
MCLK
(MHZ)
SYSCLK
(MHZ)
MCLKDIV
F2
PRESCALE
F1
R
N
K
= SYSCLK *
4 * MCLKDIV
= MCLK/
PRESCALE
= F2/F1
12
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
2
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
12
7.5264
8.192
7h
8h
86C2h
3126h
F28Bh
8FD5h
45A1h
D3A0h
6872h
3D70h
2DB4h
FD80h
1F76h
EE00h
86C2h
3126h
F28Bh
8FD5h
B0ACh
4822h
12
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
13
13
6.947446 6h
7.561846 7h
13
13
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
14.4
14.4
9.6
9.6
9.84
9.84
9.9
9.9
12
6.272
6h
6.826667 6h
9.408
10.24
9h
Ah
9.178537 9h
9.990243 9h
9.122909 9h
9.929697 9h
7.5264
8.192
7h
8h
24
12
26
13
6.947446 6h
7.561846 7h
6.690133 6h
7.281778 7h
26
13
27
13.5
13.5
27
Table 65 PLL Frequency Examples
PP, May 2008, Rev 3.1
111
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
