Pre-Production
WM8959
CSB
SCLK
SDIN
A6
A5
A4
A3
A2
A1
A0
B15
B15
B14
B14
B13
B13
B12
B12
B11
B11
B10
B10
B9
B9
B8
B8
B7
B7
B6
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
R/W
SDOUT
control register address
control register data bits (READ/WRITE)
Figure 84 4-Wire Readback (Push 0/1)
CSB
SCLK
SDIN
A6
A5
A4
A3
A2
A1
A0
B15
B15
B14
B14
B13
B13
B12
B12
B11
B11
B10
B10
B9
B9
B8
B8
B7
B7
B6
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
R/W
SDOUT
B0
undriven
ud
control register address
control register data bits (READ/WRITE)
Figure 85 4-Wire Readback (wired-OR)
PP, May 2008, Rev 3.1
115
w