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WM8955BLGECO/V 参数 Datasheet PDF下载

WM8955BLGECO/V图片预览
型号: WM8955BLGECO/V
PDF下载: 下载PDF文件 查看货源
内容描述: 立体声DAC便携式音频应用 [Stereo DAC For Portable Audio Applications]
分类和应用: 商用集成电路便携式
文件页数/大小: 44 页 / 668 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8955BL  
Production Data  
The PLL frequency ratio R = f2/f1 (see Figure 17) can be set using K and N in registers 44 (2Ch) to 46  
(2Eh):  
N = int (R)  
K = int (222 (R-N))  
Example:  
MCLK = 12MHz required clock = 12.288MHz  
R should be chosen to ensure 5<N<13. There is a divide by 4 and selectable divide by 2 after the  
PLL which should be set to meet this requirement. Enabling the divide by 2 sets the required f2 = 8x  
12.288MHz = 98.304MHz.  
R = 98.304/12 = 8.192  
N = intR = 8  
K = int (222 x (8.192-8)) = 805306 = C49BAh.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R44 (2Ch)  
N
Integer part of PLL input/output  
frequency ratio. Use values greater  
than 5 and less than 13.  
8:5  
1000  
PLL Control (1)  
K [21:18]  
K [17:9]  
Fractional part of PLL input/output  
frequency ratio (treat as one 22-digit  
binary number)  
3:0  
8:0  
0011  
024h  
R45 (2Dh)  
PLL Control (2)  
R46 (2Eh)  
K [8:0]  
KEN  
8:0  
7
1BAh  
0
PLL Control (3)  
R59 (3Bh)  
0: Fractional part (K) disabled  
1: K enabled  
Table 20 PLL Frequency Ratio Control  
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings  
are shown below.  
MCLK  
DESIRED  
OUTPUT  
(MHz)  
F2  
MCLK  
DIV2  
PLL  
OUT  
DIV2  
R
F2  
K
(MHz)  
(MHz)  
(Hex)  
(Hex)  
11.91  
11.91  
12  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7.5833  
8.2539  
7.5264  
8.192  
7
8
7
8
6
7
6
6
9
A
9
9
9
9
7
8
6
7
6
7
25545C  
103FF6  
21B089  
C49BA  
3CA2F4  
23F548  
116872  
34E818  
1A1CAC  
F5C28  
12  
13  
6.9474  
7.5618  
6.272  
13  
14.4  
14.4  
19.2  
19.2  
19.68  
19.68  
19.8  
19.8  
24  
6.8267  
9.408  
10.24  
9.1785  
9.9902  
9.1229  
9.9297  
7.5264  
8.192  
B6D22  
3F6017  
7DDCA  
3B8023  
21B089  
C49BA  
3CA2F4  
23F548  
2C2B30  
12089E  
24  
26  
6.9474  
7.5618  
6.6901  
7.2818  
26  
27  
27  
Table 21 PLL Frequency Examples  
PD Rev 4.1 February 2007  
30  
w
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