Production Data
WM8955BL
Figure 13 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a DACLRC transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 14 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the first or second rising edge of BCLK
(selectable by LRP) following a rising edge of DACLRC. Right channel data immediately follows left
channel data. Depending on word length, BCLK frequency and sample rate, there may be unused
BCLK cycles between the LSB of the right channel data and the next sample.
Figure 15 DSP Mode Audio Interface (Mode A; LRP = 0)
PD Rev 4.1 February 2007
27
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
