WM8955BL
Production Data
MCLK
MCLK
DAC SAMPLE RATE
USB
SR [4:0]
FILTER
TYPE
BCLK
MCLKDIV2=0
MCLKDIV2=1
(MS=1)
‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8711 and WM8721)
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
12.288MHz
24.576MHz
8 kHz (MCLK/1536)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00010 *
01000
1
1
1
1
1
1
3
1
1
1
1
3
1
1
1
1
1
1
3
1
1
1
1
3
01010
11100
01100 *
00000 *
01110 *
10010
11.2896MHz
18.432MHz
22.5792MHz
36.864MHz
11000
11010
10000 *
11110 *
00011 *
01001
01011
11101
01101 *
00001 *
01111 *
10011 *
11001
16.9344MHz
33.8688MHz
11011
10001 *
11111 *
USB Mode (assumes BCLKDIV2=0. ‘*’ indicates backward compatibility with WM8711 and WM8721)
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
12.000MHz
24.000MHz
8 kHz (MCLK/1500)
11.0259 kHz (MCLK/1088)
12kHz (MCLK/1000)
16kHz (MCLK/750)
1
1
1
1
1
1
1
1
1
1
1
00010 *
11001
0
1
0
0
1
0
0
1
0
3
2
01000
01010
22.0588 kHz (MCLK/544)
24kHz (MCLK/500)
11011
11100
32 kHz (MCLK/375)
01100 *
10001 *
00000 *
11111 *
01110 *
44.118 kHz (MCLK/272)
48 kHz (MCLK/250)
88.235kHz (MCLK/136)
96 kHz (MCLK/125)
Table 23 Master Clock and Sample Rates
PD Rev 4.1 February 2007
32
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
