Production Data
WM8955BL
MASTER CLOCK AND PHASE LOCKED LOOP
The WM8955BL has an on-chip phase-locked loop (PLL) circuit that can be used to:
•
generate a master clock for the WM8955BL audio function from another external clock,
e.g. in telecoms applications.
The PLL circuit is shown below.
MCLK
SEL
MCLK
DIV2
PLL
PLLOUT
DIV2
DIGITAL
CORE
MCLK
f/2
f/4
f/2
R = f2 / f1
f1
f2
Figure 17 PLL Circuit
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
MCLK Divide by 2
R8 (08h)
MCLKDIV2
6
0
Sample Rates
0: Divide disabled
1: Divide enabled
R43 (2Bh)
MCLKSEL
Select internal master clock
0: from MCLK pin
8
5
0
0
Clocking and
PLL
1: from PLL (make sure PLLEN=1)
PLL Output Divide by 2
0: Divide disabled
PLLOUTDIV2
1: Divide enabled
PLL_RB
PLLEN
0: PLL held in reset
4
3
0
0
1: PLL running (if PLLEN=1)
PLL Enable
0: PLL disabled; 1: PLL enabled.
Table 19 PLL and Clocking Control
PD Rev 4.1 February 2007
29
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
