Production Data
WM8945
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
0 = Disabled
1 = Enabled
SYSCLK Source Select
0 = MCLK
8
SYSCLK_SRC
1
1 = FLL output
SYSCLK Clock divider
7:5
SYSCLK_DIV
[2:0]
000
(Sets the scaling for either the MCLK or FLL clock
output, depending on SYSCLK_SRC)
000 = divide by 1
001 = divide by 1.5
010 = divide by 2
011 = divide by 3
100 = divide by 4
101 = divide by 6
110 = divide by 8
111 = divide by 12
TOCLK Enabled
4
TOCLK_ENA
0
(Enables timeout clock for GPIO level detection, AMU,
and PGA zero cross timeout)
0 = Disabled
1 = Enabled
BCLK Frequency (Master mode)
000 = SYSCLK
3:1
BCLK_DIV[2:0]
011
001 = SYSCLK / 2
010 = SYSCLK / 4
011 = SYSCLK / 8
100 = SYSCLK / 16
101 = SYSCLK / 32
110 = reserved
111 = reserved
Digital Audio Interface Mode select
0 = Slave mode
0
MSTR
0
1 = Master mode
Register 06h Clock Gen control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
VMID (fast-start) Enable
0 = Disabled
R7 (07h)
Additional
control
11
VMID_FAST_S
TART
0
1 = Enabled
VMID Source Select
0 = LDO supply (LDOVDD)
1 = LDO output (LDOVOUT)
VMID Ratio control
10
9
VMID_REF_SE
L
0
0
VMID_CTRL
Sets the ratio of VMID to the source selected by
VMID_REF_SEL
0 = 5/11
1 = 1/2
Start-Up Bias Enable
0 = Disabled
1 = Enabled
Bias Source select
8
7
STARTUP_BIA
S_ENA
0
0
BIAS_SRC
PD, May 2011, Rev 4.1
117
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
