WM8945
Production Data
REFER TO
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0 = Normal bias
1 = Start-Up bias
VMID soft start enable / slew rate control
00 = Disabled
6:5
VMID_RAMP
[1:0]
00
01 = Fast soft start
10 = Normal soft start
11 = Slow soft start
VMID Enable
4
VMID_ENA
SR[3:0]
0
0 = Disabled
1 = Enabled
Audio Sample Rate select
0011 = 8kHz
3:0
1101
0100 = 11.025kHz
0101 = 12kHz
0111 = 16kHz
1000 = 22.05kHz
1001 = 24kHz
1011 = 32kHz
1100 = 44.1kHz
1101 = 48kHz
Register 07h Additional control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
FLL Clock Reference Divider
00 = MCLK / 1
R8 (08h)
FLL Control
1
12:11 FLL_CLK_REF
_DIV[1:0]
00
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must be divided down
to <=13.5MHz.
For lower power operation, the reference clock can be
divided down further if desired.
FOUT clock divider
000 = 2
10:8
FLL_OUTDIV
[2:0]
001
001 = 4
010 = 8
011 = 16
100 = 32
101 = 64
110 = 128
111 = 256
(FOUT = FVCO / FLL_OUTDIV)
Frequency of the FLL control block
000 = FVCO / 1 (Recommended value)
001 = FVCO / 2
7:5
FLL_CTRL_RA
TE[2:0]
000
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
PD, May 2011, Rev 4.1
118
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
