Production Data
WM8945
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
111 = FVCO / 8
Recommended that this register is not changed from
default.
FVCO clock divider
000 = 1
4:2
FLL_FRATIO
[2:0]
000
001 = 2
010 = 4
011 = 8
1XX = 16
000 recommended for FREF > 1MHz
100 recommended for FREF < 16kHz
011 recommended for all other cases
Fractional enable
1
FLL_FRAC
1
0 = Integer Mode
1 = Fractional Mode
Integer mode offers reduced power consumption.
Fractional mode offers best FLL performance, provided
also that N.K is a non-integer value.
FLL Enable
0 = Disabled
1 = Enabled
0
FLL_ENA
0
Register 08h FLL Control 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Fractional multiply for FREF
(MSB = 0.5)
R9 (09h)
FLL Control
2
15:0
FLL_K[15:0]
0011_0001
_0010_011
1
Register 09h FLL Control 2
REGISTER
ADDRESS
BIT
14:5
3:0
LABEL
DEFAULT
DESCRIPTION
REFER TO
Integer multiply for FREF
(LSB = 1)
R10 (0Ah)
FLL Control
3
FLL_N[9:0]
00_0000_1
000
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
FLL_GAIN[3:0]
0100
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that this register is not changed from
default.
Register 0Ah FLL Control 3
PD, May 2011, Rev 4.1
119
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
