WM8945
Production Data
REFER TO
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
11 = 32 bits
Note – see “Companding” for the selection of 8-bit
mode.
Digital Audio Interface Format
00 = Reserved
1:0
FMT[1:0]
10
01 = Left Justified
10 = I2S format
11 = DSP/PCM mode
Register 04h Audio Interface
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Digital Loopback Function
0 = No loopback
R5 (05h)
Companding
control
5
LOOPBACK
0
1 = Loopback enabled (ADC data output is directly input
to DAC data input).
DAC Companding Enable
0 = Disabled
3
2
1
0
DAC_COMP
0
0
0
0
1 = Enabled
DAC Companding Mode
0 = µ-law
DAC_COMPM
ODE
1 = A-law
ADC Companding Enable
0 = Disabled
ADC_COMP
1 = Enabled
ADC Companding Mode
0 = µ-law
ADC_COMPM
ODE
1 = A-law
Register 05h Companding control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Oscillator Enable
0 = Disabled
R6 (06h)
Clock Gen
control
15
OSC_CLK_EN
A
0
1 = Enabled
This needs to be set when doing AUXADC
measurements, or when a timeout clock is required for
PGA zero cross or GPIO input detection
MCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
14:13
MCLK_PULL
[1:0]
00
10 = pull-up
11 = reserved
CLKOUT Source Select
0 = SYSCLK
12
CLKOUT_SEL
0
1 = FLL or MCLK (set by SYSCLK_SRC register)
CLKOUT Clock divider
00 = divide by 1
11:10
CLKOUT_DIV
[1:0]
00
01 = divide by 2
10 = divide by 4
11 = divide by 8
SYSCLK Enable
9
SYSCLK_ENA
0
PD, May 2011, Rev 4.1
116
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
