Production Data
WM8945
REGISTER BITS BY ADDRESS
The complete register map is shown below. The detailed description can be found in the relevant text of the device description.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Writing to this register resets all registers to their default
state.
R0 (00h)
Software
Reset/Chip
ID 1
15:0
SW_RESET[15 0110_0010
:0]
_0010_100
1
Reading from this register will indicate device family ID
6229h.
Register 00h Software Reset/Chip ID 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Reading from this register will indicate the Revision ID.
R1 (01h)
Chip ID 2
3:0
CHIP_REV[3:0]
0000
Register 01h Chip ID 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Left Input PGA Enable
0 = Disabled
R2 (02h)
Power
managemen
t 1
12
INPPGAL_ENA
0
1 = Enabled
Left ADC Enable
0 = Disabled
10
ADCL_ENA
DMIC_ENA
0
0
1 = Enabled
ADCL_ENA must be set to 1 when processing left
channel data from the ADC or Digital Microphone.
Enables Digital Microphone mode
0 = Audio DSP input is from ADC
7
1 = Audio DSP input is from digital microphone
interface
When DMIC_ENA = 0, the Digital microphone clock
(DMICCLK) is held low.
Microphone Bias Enable
0 = Disabled
4
3
2
MICB_ENA
BIAS_ENA
0
0
0
1 = Enabled
Master Bias Enable
0 = Disabled
1 = Enabled
VMID Buffer Enable.
VMID_BUF_EN
A
(The buffered VMID may be applied to disabled input
and output pins.)
0 = Disabled
1 = Enabled
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50k divider (for normal operation)
10 = 2 x 250k divider (for low power standby)
11 = 2 x 5k divider (for fast start-up)
1:0
VMID_SEL[1:0]
00
Register 02h Power management 1
PD, May 2011, Rev 4.1
113
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
