Production Data
WM8945
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DACR_ENA must be set to 1 when processing right
channel data from the DAC or Digital Beep Generator.
Left DAC Enable
0 = Disabled
1 = Enabled
0
DACL_ENA
0
DACR_ENA must be set to 1 when processing left
channel data from the DAC or Digital Beep Generator.
Register 03h Power management 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R4 (04h)
Audio
Interface
15:14 DACDATA_PU
LL[1:0]
00
DACDAT pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
10 = pull-up
11 = reserved
LRCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
13:12 FRAME_PULL
[1:0]
00
00
10 = pull-up
11 = reserved
BCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
11:10
BCLK_PULL
[1:0]
10 = pull-up
11 = reserved
Right Digital Audio interface source
0 = Left ADC data is output on right channel
1 = No data is output on right channel
Left Digital Audio interface source
0 = Left ADC data is output on left channel
1 = No data is output on left channel
Left DAC Data Source Select
0 = Left DAC outputs left interface data
1 = Left DAC outputs right interface data
BCLK Invert
9
8
6
5
4
ADCR_SRC
ADCL_SRC
DACL_SRC
BCLK_INV
LRCLK_INV
1
0
0
0
0
0 = BCLK not inverted
1 = BCLK inverted
LRCLK Polarity / DSP Mode A-B select.
Right, left and I2S modes – LRCLK polarity
0 = Not Inverted
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK rising edge after
LRCLK rising edge (mode A)
1 = MSB is available on 1st BCLK rising edge after
LRCLK rising edge (mode B)
Digital Audio Interface Word Length
00 = 16 bits
3:2
WL[1:0]
10
01 = 20 bits
10 = 24 bits
PD, May 2011, Rev 4.1
115
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
