WM8912
Production Data
POWER-ON RESET
The WM8912 includes an internal Power-On-Reset (POR) circuit, which is used to reset the digital
logic into a default state after power up. The POR circuit is powered from AVDD and monitors
DCVDD. The internal P¯ ¯O¯R signal is asserted low when AVDD and DCVDD are below minimum
thresholds.
The specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages.
Typical scenarios are illustrated in Figure 54 and Figure 55.
AVDD
Vpora
Vpora_off
0V
DCVDD
0V
Vpord_on
HI
Internal POR
LO
POR active
POR active
Device ready
POR undefined
Figure 54 Power On Reset Timing - AVDD Enabled First
Figure 55 Power On Reset Timing - DCVDD Enabled First
PD, Rev 4.0, September 2010
90
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
