欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8912GEFL/RV 参数 Datasheet PDF下载

WM8912GEFL/RV图片预览
型号: WM8912GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗DAC与耳机驱动器的便携式音频应用 [Ultra Low Power DAC with Headphone Driver for Portable Audio Applications]
分类和应用: 驱动器便携式
文件页数/大小: 128 页 / 1259 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8912GEFL/RV的Datasheet PDF文件第84页浏览型号WM8912GEFL/RV的Datasheet PDF文件第85页浏览型号WM8912GEFL/RV的Datasheet PDF文件第86页浏览型号WM8912GEFL/RV的Datasheet PDF文件第87页浏览型号WM8912GEFL/RV的Datasheet PDF文件第89页浏览型号WM8912GEFL/RV的Datasheet PDF文件第90页浏览型号WM8912GEFL/RV的Datasheet PDF文件第91页浏览型号WM8912GEFL/RV的Datasheet PDF文件第92页  
WM8912  
Production Data  
WSEQ  
INDEX  
REGISTER  
ADDRESS  
WIDTH  
START  
DATA  
DELAY  
EOS  
DESCRIPTION  
(delay = 0.5625ms)  
16 (10h)  
R67 (43h)  
4 bits  
Bit 0  
0Fh  
Ch  
0b  
DCS_ENA_CHAN_0 = 1  
DCS_ENA_CHAN_1 = 1  
DCS_ENA_CHAN_2 = 1  
DCS_ENA_CHAN_3 = 1  
(delay = 0.5625ms)  
17 (11h)  
R68 (44h)  
8 bits  
Bit 0  
F0h  
0h  
0b  
DCS_TRIG_STARTUP_0 = 1  
DCS_TRIG_STARTUP_1 = 1  
DCS_TRIG_STARTUP_2 = 1  
DCS_TRIG_STARTUP_3 = 1  
(delay = 256.5ms)  
18 (12h)  
19 (13h)  
R255 (FFh)  
R90 (5Ah)  
1 bit  
Bit 0  
Bit 0  
00h  
77h  
0h  
0h  
0b  
0b  
Dummy Write for expansion  
(delay = 0.5625ms)  
8 bits  
HPL_ENA_OUTP = 1  
HPR_ENA_OUTP = 1  
(delay = 0.5625ms)  
20 (14h)  
21 (15h)  
22 (16h)  
R94 (5Eh)  
R90 (5Ah)  
R94 (5Eh)  
8 bits  
8 bits  
8 bits  
Bit 0  
Bit 0  
Bit 0  
77h  
FFh  
FFh  
0h  
0h  
0h  
0b  
0b  
1b  
LINEOUTL_ENA_OUTP = 1  
LINEOUTR_ENA_OUTP = 1  
(delay = 0.5625ms)  
HPL_RMV_SHORT = 1  
HPR_RMV_SHORT = 1  
(delay = 0.5625ms)  
LINEOUTL_RMV_SHORT = 1  
LINEOUTR_RMV_SHORT = 1  
End of Sequence  
23 (17h)  
24 (18h)  
R255 (FFh)  
R255 (FFh)  
1 bit  
1 bit  
Bit 0  
Bit 0  
00h  
00h  
0h  
0h  
0b  
0b  
Spare  
Spare  
Table 59 Start-up Sequence  
SHUTDOWN SEQUENCE  
The Shutdown sequence is initiated by writing 0119h to Register R111 (6Fh). This single operation  
starts the Control Write Sequencer at Index Address 25 (19h) and executes the sequence defined in  
Table 60.  
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately  
350ms to run.  
WSEQ  
INDEX  
REGISTER  
ADDRESS  
WIDTH  
START  
DATA  
DELAY  
EOS  
DESCRIPTION  
25 (19h)  
26 (1Ah)  
27 (1Bh)  
R94 (5Eh)  
R90 (5Ah)  
R90 (5Ah)  
8 bits  
Bit 0  
77h  
0h  
0b  
LINEOUTL_RMV_SHORT = 0  
LINEOUTR_RMV_SHORT = 0  
(delay = 0.5625ms)  
8 bits  
8 bits  
Bit 0  
Bit 0  
77h  
00h  
0h  
0h  
0b  
0b  
HPL_RMV_SHORT = 0  
HPR_RMV_SHORT = 0  
(delay = 0.5625ms)  
HPL_ENA_OUTP = 0  
HPL_ENA_DLY = 0  
HPL_ENA = 0  
HPR_ENA_OUTP = 0  
HPR_ENA_DLY = 0  
HPR_ENA = 0  
(delay = 0.5625ms)  
PD, Rev 4.0, September 2010  
88  
w
 复制成功!