Production Data
WM8912
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
4:0
BCLK_DIV
[4:0]
0_0100
BCLK Frequency (Master Mode)
00000 = SYSCLK
00001 = SYSCLK / 1.5
00010 = SYSCLK / 2
00011 = SYSCLK / 3
00100 = SYSCLK / 4
00101 = SYSCLK / 5
00110 = SYSCLK / 5.5
00111 = SYSCLK / 6
01000 = SYSCLK / 8 (default)
01001 = SYSCLK / 10
01010 = SYSCLK / 11
01011 = SYSCLK / 12
01100 = SYSCLK / 16
01101 = SYSCLK / 20
01110 = SYSCLK / 22
01111 = SYSCLK / 24
10000 = SYSCLK / 25
10001 = SYSCLK / 30
10010 = SYSCLK / 32
10011 = SYSCLK / 44
10100 = SYSCLK / 48
Register 1Ah Audio Interface 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R27 (1Bh)
Audio
Interface 3
11
LRCLK_DIR
0
Audio Interface LRC Direction
0 = LRC is input
1 = LRC is output
10:0
LRCLK_RATE 000_0100_ LRC Rate (Master Mode)
[10:0]
0000
LRC clock output = BCLK / LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
Register 1Bh Audio Interface 3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R30 (1Eh)
DAC Digital
Volume Left
8
DAC_VU
0
DAC Volume Update
Writing a 1 to this bit causes left and right DAC volume
to be updated simultaneously
7:0
DACL_VOL
[7:0]
1100_0000 Left DAC Digital Volume
00h = Mute
01h = -71.625dB
02h = -71.250dB
… (0.375dB steps)
C0h to FFh = 0dB
Register 1Eh DAC Digital Volume Left
PD, Rev 4.0, September 2010
101
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
