WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R18 (12h)
Power
Managemen
t 6
3
DACL_ENA
0
Left DAC Enable
0 = DAC disabled
1 = DAC enabled
Right DAC Enable
0 = DAC disabled
1 = DAC enabled
2
DACR_ENA
0
Register 12h Power Management 6
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R20 (14h)
Clock Rates
0
14
TOCLK_RATE
_DIV16
0
TOCLK Rate Divider (/16)
0 = f / 1
1 = f / 16
13
0
TOCLK_RATE
_X4
0
0
TOCLK Rate Multiplier
0 = f x 1
1 = f x 4
MCLK_DIV
Enables divide by 2 on MCLK
0 = SYSCLK = MCLK
1 = SYSCLK = MCLK / 2
Register 14h Clock Rates 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R21 (15h)
Clock Rates
1
13:10 CLK_SYS_RA
TE [3:0]
0011
Selects the SYSCLK / fs ratio
0000 = 64
0001 = 128
0010 = 192
0011 = 256
0100 = 384
0101 = 512
0110 = 768
0111 = 1024
1000 = 1408
1001 = 1536
2:0
SAMPLE_RAT
E [2:0]
101
Selects the Sample Rate (fs)
000 = 8kHz
001 = 11.025kHz, 12kHz
010 = 16kHz
011 = 22.05kHz, 24kHz
100 = 32kHz
101 = 44.1kHz, 48kHz
110 to 111 = Reserved
Register 15h Clock Rates 1
PD, Rev 4.0, September 2010
98
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
