WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R25 (19h)
Audio
Interface 1
13
AIFDAC_TDM
0
DAC TDM Enable
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
Audio Interface Tristate
12
8
AIFDAC_TDM_
CHAN
0
0
0
0
0
AIF_TRIS
AIF_BCLK_INV
BCLK_DIR
0 = Audio interface pins operate normally
1 = Tristate all audio interface pins
BCLK Invert
7
0 = BCLK not inverted
1 = BCLK inverted
6
Audio Interface BCLK Direction
0 = BCLK is input
1 = BCLK is output
4
AIF_LRCLK_IN
V
LRC Polarity / DSP Mode A-B select.
Right, left and I2S modes – LRC polarity
0 = Not Inverted
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK rising edge after
LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising edge after
LRC rising edge (mode B)
3:2
1:0
AIF_WL [1:0]
AIF_FMT [1:0]
10
10
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Digital Audio Interface Format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = DSP
Register 19h Audio Interface 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R26 (1Ah)
Audio
Interface 2
11:8
OPCLK_DIV
[3:0]
0000
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
PD, Rev 4.0, September 2010
100
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
