Pre-Production
WM8904
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
TOCLK Rate Divider (/16)
REFER TO
Clocking and
Sample Rates
R20 (14h)
Clock Rates
0
14
TOCLK_RATE
_DIV16
0
0 = f / 1
1 = f / 16
TOCLK Rate Multiplier
0 = f x 1
Clocking and
Sample Rates
13
0
TOCLK_RATE
_X4
0
0
1 = f x 4
Enables divide by 2 on MCLK
0 = SYSCLK = MCLK
1 = SYSCLK = MCLK / 2
Clocking and
Sample Rates
MCLK_DIV
Register 14h Clock Rates 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Selects the SYSCLK / fs ratio
0000 = 64
Clocking and
Sample Rates
R21 (15h)
Clock Rates
1
13:10 CLK_SYS_RAT
E [3:0]
0011
0001 = 128
0010 = 192
0011 = 256
0100 = 384
0101 = 512
0110 = 768
0111 = 1024
1000 = 1408
1001 = 1536
Selects the Sample Rate (fs)
000 = 8kHz
Clocking and
Sample Rates
2:0
SAMPLE_RAT
E [2:0]
101
001 = 11.025kHz, 12kHz
010 = 16kHz
011 = 22.05kHz, 24kHz
100 = 32kHz
101 = 44.1kHz, 48kHz
110 to 111 = Reserved
Register 15h Clock Rates 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
MCLK Invert
Clocking and
Sample Rates
R22 (16h)
Clock Rates
2
15
MCLK_INV
0
0 = MCLK not inverted
1 = MCLK inverted
SYSCLK Source Select
0 = MCLK
Clocking and
Sample Rates
14
12
3
SYSCLK_SRC
TOCLK_RATE
OPCLK_ENA
0
0
0
0
1 = FLL output
TOCLK Rate Divider (/2)
0 = f / 2
Clocking and
Sample Rates
1 = f / 1
GPIO Clock Output Enable
0 = disabled
Clocking and
Sample Rates
1 = enabled
System Clock enable
0 = Disabled
Clocking and
Sample Rates
2
CLK_SYS_EN
A
1 = Enabled
PP, Rev 3.3, September 2012
145
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
