Pre-Production
WM8904
SHUTDOWN SEQUENCE
The Shutdown sequence is initiated by writing 0119h to Register R111 (6Fh). This single operation
starts the Control Write Sequencer at Index Address 25 (19h) and executes the sequence defined in
Table 89.
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately 350ms
to run.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
8 bits
Bit 0
77h
0h
0b
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
(delay = 0.5625ms)
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
(delay = 0.5625ms)
HPL_ENA_OUTP = 0
HPL_ENA_DLY = 0
HPL_ENA = 0
25 (19h)
26 (1Ah)
27 (1Bh)
R94 (5Eh)
8 bits
8 bits
Bit 0
Bit 0
77h
00h
0h
0h
0b
0b
R90 (5Ah)
R90 (5Ah)
HPR_ENA_OUTP = 0
HPR_ENA_DLY = 0
HPR_ENA = 0
(delay = 0.5625ms)
LINEOUTL_ENA_OUTP = 0
LINEOUTL_ENA_DLY = 0
LINEOUTL_ENA = 0
LINEOUTR_ENA_OUTP = 0
LINEOUTR_ENA_DLY = 0
LINEOUTR_ENA = 0
(delay = 0.5625ms)
DCS_ENA_CHAN_0 = 0
DCS_ENA_CHAN_1 = 0
DCS_ENA_CHAN_2 = 0
DCS_ENA_CHAN_3 = 0
(delay = 0.5625ms)
CP_ENA = 0
8 bits
Bit 0
00h
0h
0b
28 (1Ch)
R94 (5Eh)
4 bits
Bit 0
00h
0h
0b
29 (1Dh)
R67 (43h)
1 bit
Bit 0
Bit 2
00h
00h
0h
0h
0b
0b
30 (1Eh)
31 (1Fh)
R98 (62h)
R18 (12h)
(delay = 0.5625ms)
DACL_ENA = 0
2 bits
DACR_ENA = 0
(delay = 0.5625ms)
CLK_DSP_ENA = 0
(delay = 0.5625ms)
HPL_PGA_ENA = 0
HPR_PGA_ENA = 0
(delay = 0.5625ms)
LINEOUTL_PGA_ENA = 0
LINEOUTR_PGA_ENA = 0
(delay = 0.5625ms)
BIAS_ENA = 0
1 bit
Bit 1
Bit 0
00h
00h
0h
0h
0b
0b
32 (20h)
33 (21h)
R22 (16h)
R14 (0Eh)
2 bits
2 bits
Bit 0
00h
0h
0b
34 (22h)
R15 (0Fh)
1 bit
1 bit
1 bit
8 bits
Bit 0
Bit 0
Bit 0
Bit 0
00h
00h
00h
00h
0h
Ch
9h
0h
0b
0b
0b
0b
35 (23h)
36 (24h)
37 (25h)
38 (26h)
R4 (04h)
R5 (05h)
R5 (05h)
R5 (05h)
(delay = 0.5625ms)
VMID_ENA = 0
(delay = 256.5ms)
VMID_ENA = 0
(delay = 32.5ms)
VMID_BUF_ENA = 0
PP, Rev 3.3, September 2012
131
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
