Pre-Production
WM8904
POWER-ON RESET
The WM8904 includes an internal Power-On-Reset (POR) circuit, which is used to reset the digital
logic into a default state after power up. The POR circuit is powered from AVDD and monitors
DCVDD. The internal P¯O¯¯R signal is asserted low when AVDD or DCVDD are below minimum
thresholds.
The specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages.
Typical scenarios are illustrated in Figure 69 and Figure 70.
AVDD
Vpora
Vpora_off
0V
DCVDD
0V
Vpord_on
HI
Internal POR
LO
POR active
POR active
Device ready
POR undefined
Figure 69 Power On Reset timing - AVDD enabled first
AVDD
Vpora
Vpora_on
0V
DCVDD
0V
Vpord_off
HI
Internal POR
LO
POR active
Device ready
POR active
POR undefined
Figure 70 Power On Reset timing - DCVDD enabled first
PP, Rev 3.3, September 2012
133
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
