WM8850
Pre-Production
Test Conditions
AVDD = CPVDD = 5V, DBVDD = 3.3V, DCVDD = 1.8V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
S/PDIF Receiver Specification
Input Signal Level
IEC-60958 Compatible Input Mode
Normal CMOS Compatible Input Mode
Low-Amplitude CMOS Compatible Input Mode
Normal CMOS Compatible Input Mode
Low-Amplitude CMOS Compatible Input Mode
IEC-60958 Compatible Input Mode
200
500
mVp-p
V
0.7 *
DBVDD
Input Signal Logic High
VIH(S/PDIF)
0.4 *
DBVDD
1.8
V
0.3 *
DBVDD
V
Input Signal Logic Low
Input Pin Bias Voltage
Input Impedance
VIL(S/PDIF)
DBVDD
x 0.2
V
0.5 *
DCVDD
V
IEC-60958 Compatible Input Mode
7.5
kΩ
kΩ
mV
mV
mV
ppm
%
ZIN
Normal CMOS Compatible Input Mode
IEC-60958 Compatible Input Mode
100
Input Hysteresis
50
Normal CMOS Compatible Input Mode
Low-Amplitude CMOS Compatible Input Mode
300
150
10000
+1
Input Sample Rate Lock
Tolerance
Includes maximum reference clock error of
±0.025% as allowed by HDA Specification
-1
192
Lock Delay
3
Frame
Blocks
S/PDIF Stream Jitter
Tolerance
UI = 1/fs(in)
10
UI
32
44.1
48
Input Sample Rate
Support
kHz
88.2
96
PP, April 2011, Rev 3.2
22
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
