WM8850
Pre-Production
SIGNAL TIMING REQUIREMENTS
Signal timing requirements are as defined in the High Definition Audio Specification Revision 1.0,
section 6.2.3.1. This section of the specification is repeated here for completeness.
Test Conditions
DBVDD=3.3V, AVDD=CPVDD=5V, DCVDD=1.8V, TA=+25°C
PARAMETER
SYMBOL
MIN
41.163
17.5
TYP
MAX
UNIT
ns
Period of BCLK including jitter
T_cyc
T_high
T_low
41.67
42.171
High phase of BCLK
ns
Low phase of BCLK
17.5
ns
BCLK jitter
150
500
11
ps
Time after rising edge of BCLK that SDI becomes valid
Setup for SDO at both rising and falling edge of BCLK
Hold for SDO at both rising and falling edge of BCLK
Table 1 High Definition Audio Link I/O Signal Timing
T_tco
T_su
T_h
3
5
5
ns
ns
ns
Notes:
1. Measurement points are as defined in the High Definition Audio Specification Revision 1.0 at either 0.35*DBVDD, 0.5*DBVDD
or 0.65*DBVDD as appropriate
2. Period specification for BCLK is the long term average frequency measured over 1ms. BCLK has a 100ppm tolerance in the
High Definition Audio Architecture
3. 42/58% is the worst case BCLK duty cycle at the WM8850
4. The WM8850 meets the timing requirements with the slew rate of the inputs in the range of 1V/ns to 3V/ns
PP, April 2011, Rev 3.2
w
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
