WM8850
Pre-Production
Test Conditions
AVDD = CPVDD = 5V, DBVDD = 3.3V, DCVDD = 1.8V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output 1 (VOUT1L, VOUT1R)
RL = 1kΩ
to 47kΩ
2 x
AVDD/5
VRMS
H-Phn
Enable = 0
Full Scale Output Signal
Level
VOUT
RL = 16Ω
to 1kΩ
0.8 x
AVDD/5
VRMS
mW
H-Phn
Enable = 1
Maximum Rated Output
POUT(max)
RL = 16Ω
40
Power
Load Impedance
Load Capacitance
DC Offset
RL
CL
16
-1
47k
1
Ω
nF
mV
Measured between VOUT1L/R and AGND with
path fully enabled but no signal playing
0
+1
Analogue Output 2 (VOUT2L, VOUT2LN, VOUT2RP, VOUT2RN)
Differential Full Scale
Output Signal Level
RL = 5kΩ
to 47kΩ
2 x
AVDD/5
VOUT
VRMS
Single-ended Full Scale
Output Signal Level
RL = 5kΩ
to 47kΩ
1 x
AVDD/5
VOUT
VRMS
Load Impedance
Load Capacitance
RL
CL
5
47
1
kΩ
nF
Analogue Output 3 (VOUT3L, VOUT3LN, VOUT3RP, VOUT3RN)
Differential Full Scale
Output Signal Level
RL = 5kΩ
to 47kΩ
2 x
AVDD/5
VOUT
VRMS
Single-ended Full Scale
Output Signal Level
RL = 5kΩ
to 47kΩ
1 x
AVDD/5
VOUT
VRMS
Load Impedance
Load Capacitance
RL
CL
5
47
1
kΩ
nF
PP, April 2011, Rev 3.2
18
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
