WM8802
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Digital audio input/output setting:
REGISTER ADDRESS
CCB address: 0xE8;
Command address: 11
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
1
0
1
1
0
0
CAU
CAL
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
0
0
TXMOD1 TXMOD0
TXMUT
TDTSEL
TXLRP
TXDFS
TXDFS
TXLRP
TDATA input data format setting
0: I2S data input (initial value)
1: MSB-first front-loading data input
TLRCK input clock polarity setting
0: Low period: L-channel data; High period: R-channel data (initial
value)
1: Low period: R-channel data; High period: L-channel data
TDTSEL
Input data setting
0: TDATA input data (initial value)
1: SDIN input data
TXMUT
TXO output setting
0: Conversion data output (initial value)
1: Low fixed output
TXMOD [1:0]
Mode setting
00: Normal operation (L-channel, R-channel stereo mode) (initial value)
01: L-channel continuous (time-division mode)
10: R-channel continuous (time-division mode)
11: reserved
CHANNEL STATUS DATA WRITE
CCB address is set to 0xE9 for channel status data write in the modulation function.
DI0 to DI7 are not channel status bits. Always input a chip address to DI0 and DI1. Input "0" to DI2,
DI3 and DI7 because they are reserved for the system. Select the channel status data write length
with DI4 to DI6. Up to 48 bits can be set, in 8-bit units.
After CE becomes Low, input data is written from preamble B.
INPUT TABLE DATA
RANGE
INPUT TABLE DATA
RANGE
DI6
DI5
DI4
DI6
DI5
DI4
0
0
0
0
0
0
1
1
0
1
0
1
Bit 0 to bit 7
1
1
1
1
0
0
1
1
0
1
0
1
Bit 0 to bit 39
Bit 0 to bit 15
Bit 0 to bit 23
Bit 0 to bit 31
Bit 0 to bit 47
Reserved
Reserved
Table 18 Relation between Input Data Length Setting Register and Data Length
PP Rev 1.1 April 2004
52
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
