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WM8802
INT output contents setting:
REGISTER ADDRESS
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
CCB address: 0xE8;
Command address: 8
1
0
0
0
0
0
CAU
CAL
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
EMPF
SLIPO
PCRNW
UNPCM
CSRNW
FSCHG
INDET
ERROR
ERROR
INDET
RERR signal output setting
0: Do not output. (initial value)
1: Output RERR pin status change.
Input data detection output setting
0: Do not output. (initial value)
1: Output input data pin status change.
FSCHG
CSRNW
UNPCM
PCRNW
SLIPO
PLL lock frequency calculation result update flag output setting
0: Do not output. (initial value)
1: Output PLL lock frequency calculation result update flag.
First 48 channel status bits update flag output setting
0: Do not output. (initial value)
1: Output first 48 channel status bits update flag.
Non-PCM data detection change flag output setting
0: Do not output. (initial value)
1: Output AUDIO pin status change.
Burst preamble Pc update flag output setting
0: Do not output. (initial value)
1: Output burst preamble Pc update flag.
Slip signal output setting during slave operation
0: Do not output. (initial value)
1: Read data output twice and output data loss detection flag.
EMPF
Emphasis detection flag output setting
0: Do not output. (initial value)
1: Output emphasis detection flag.
The channel status update flag compares the first 48 bits of data of the previous block with those of
the current block and a flag is output when they are the same.
The burst preamble Pc update flag also compares the 16 bits of data of the previous block with those
of the current data and an update flag is output if they match.
PP Rev 1.1 April 2004
49
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
